1. Field of the Invention
The present invention relates to an extended graphics array (XGA) graphics system, and more particularly, to an XGA graphics system in which data received into a double memory bank is converted into a single memory bank.
2. Description of the Related Art
FIG. 13 is a block diagram showing a structure of a conventional graphics system. A PC-SET 131 is a computer having an XGA graphics card which generates control signals and a data signal, which are for an XGA graphics mode. Here, the control signals are a vertical synchronizing signal (Vsync), a horizontal synchronizing signal (Hsync), a data enable signal (DE), and a main clock (MCLK). The data signal, which includes pixel data to be displayed on a screen, is divided into even-number data (IN.sub.-- B) and odd-number data (IN.sub.-- A) when transmitted.
An interface unit (I/F IC) 133 controls three drive units, e.g., a gate drive unit (GATE IC) 137, an up-source drive unit (UP-SOURCE IC) 138, and a down-source drive unit (DOWN-SOURCE IC) 139 according to the control signals and the data signal transmitted from PC-SET 131. Interface unit (I/F IC) 133 transmits IN.sub.-- B to up-source drive unit (UP-SOURCE IC) 138 and IN.sub.-- A to down-source drive unit (DOWN-SOURCE IC) 139. An LCD panel 135 is driven by gate drive unit (GATE IC) 137, up-source drive unit (UP-SOURCE IC) 138, and down-source drive unit (DOWN-SOURCE IC) 139.
FIG. 14 is a view for illustrating operation of the conventional interface unit (I/F IC) 133 of FIG. 13. The even-number data IN.sub.-- B is sequentially transmitted to source drive unit (UP-SOURCE IC) 138 through flip-flops 141, and the odd-number data IN.sub.-- A is sequentially transmitted to the down-source drive unit (DOWN-SOURCE IC) 139 through flip-flops 142. Here, the data transmission is synchronized by main clock MCLK. LCD panel 135 is driven by up-source drive unit (UP-SOURCE IC) 138 and down-source drive unit (DOWN-SOURCE IC) 139.
Accordingly, the conventional graphics system is appropriate for a circuit which sequentially outputs sequentially received data, but inappropriate for a circuit which temporarily stores the data or outputs the data regardless of order. Also, since the data is processed by main clock MCLK which has a high frequency, the probability of electromagnetic interference is high. Moreover, a great deal of power is consumed due to the many state transitions of main clock MCLK.